1. Field of the Invention
This disclosure relates generally to layout designing for semiconductor circuits, and more specifically to routing circuit elements such as Fin Field Effect Transistors (FinFETs) using an interactive user interface.
2. Description of Related Art
Circuit layout designing is often performed during a chip design process. Some circuit layout design tools use Follow-The-Cursor (FTC) interactive routing approach that allows users to draw routing connections from a transistor by moving a cursor on a screen. Such circuit layout design tools may first draw a horizontal trunk and then draw individual connections to the MOSFET transistors' gates, sources, or drains based on user input.
Circuit designs including FinFETs, however, pose a new challenge to such FTC interactive routing approach. When FinFETs are used in circuit designs, tens or even hundreds of connections are made to or from a single row of FinFETs. It is very time consuming and inefficient to make such connections to or from FinFETs by individual manual mouse clicks. Some existing solutions such as point-to-point interactive routers (also known as “guided routing routers”) may be applied. But even such point-to-point interactive routers are limited in application since the actual routing results are only instantiated on the last mouse click. In addition, non-interactive routing tools like batch routers do not to afford the fine-grained controls to the users for creating interconnections that precisely match what the users intend.
Furthermore, connections made for a row of FinFETs are typically duplicated in other rows FinFETs or applied in the same form or in a modified form. However, it is difficult for the users to know in advance whether a specific connection for a FinFET can be successfully duplicated to another FinFET in the same form or in a modified form without causing any conflicts with other components or connections in a circuit. Accordingly, many rounds of iterations may be repeated before a viable configuration applicable to all FinFETs can be achieved, resulting in waste in time and cost.